Field effect transistors are comprised of a pair of diffusion regions, referred to as a source and a drain, spaced apart within a semiconductive substrate. The transistors include a gate provided adjacent the substrate separation region between the diffusion regions for imparting an electric field to enable current to flow between the diffusion regions. The substrate material adjacent the gate and between the diffusion regions is referred to as the channel. The semiconductive substrate typically comprises a bulk monocrystalline silicon substrate having a light conductivity dopant impurity concentration. Alternately, the substrate can be provided in the form of a thin layer of lightly doped semiconductive material over an underlying insulating layer. Such are commonly referred to as semiconductor-on-insulator (SOI) constructions.
Integrated circuitry fabrication technology continues to strive to increase circuit density, and thereby minimize the size and channel lengths of field effect transistors. Improvements in technology have resulted in reduction of field effect transistor size from long-channel devices (i.e., channel lengths greater than 2 microns) to short-channel devices (i.e., channel lengths less than 2 microns). As field effect transistor channel lengths (i.e., gate lenghts or wordline widths) became smaller than about 2 microns, so-called short channel effects began to become increasingly significant. As a result, device design and consequently process technology had to be modified to take these effects into account so that optimum device performance could continue to be obtained. For example, the lateral electrical field in the channel region increases as a result of smaller transistor channel length as the supply voltage remains constant. If the field becomes strong enough, it can give rise to so-called hot-carrier effects. Hot-carrier effects often lead to gate oxide degradation, as these energetic carriers can be injected into gate oxide and become permenant charges.
A recognized prior art solution to this problem is to subject the poly gate after its formation to a thermal oxidation step. Such will effectively reoxidize the source and drain regions as well as grow a layer of thermal oxide on the gate sidewalls. The oxidation has the effect of rounding the poly gate edge corners in effectively oxidizing a portion of the gate and underlying substrate, thereby increasing the thickness of the gate oxide layer at least at the edges of the gate. Such reduces the gate-to-drain overlap capacitance and strengthens the gate oxide at the polysilicon gate edge. The latter benefits are effectively obtained because oxidation-induced encroachment gives rise to a graded gate oxide under the polysilicon edge. The thicker oxide at the gate edge relieves the electric-field intensity at the corner of the gate structure, thus reducing short channel effects.
The prior art technique for accomplishing such reoxidation is similar to the conventional wet and dry oxidation at atmoshperic pressure and at a temperature of 800.degree. C. or greater. The typical process exposure is for 10 minutes to grow a layer of oxide of from 50 to 200 Angstroms thick on the sidewalls of the patterned gate.
Another method which addresses hot-carrier effects is provision of lightly doped drain (LDD) regions within the substrate relative to the channel region in advance of the source and drain regions. The LDD regions are provided to be lighter conductively doped (i.e., less concentration) than the source and drain regions. This facilitates sharing of the voltage drop by the drain and the channel, as opposed to the stark voltage drop at the channel occurring in non-LDD n-type transistors. The LDD regions absorb some of the voltage drop potential into the drain, thus effectively eliminating hot carrier effects. As a result, the stability of the device is increased.
However, further shrinking of the gate length (i.e., shorter channel length) can lead to sufficient lateral diffusion of LDD and other dopants across the channel. Diffusion of a given material is in large part temperature driven, and the conventional reoxidation process for oxidizing the gate sidewalls as described above undesirably exacerbates this undesired diffusion.